Exemplary embodiments of the present invention relate to a semiconductor device, and more particularly, to a clock signal generation circuit.
Generally, a semiconductor device produces internal clock signals using an external clock signal and uses these internal clock signals as reference clock signals for synchronization with various operation timings. Accordingly, a clock signal generation circuit for generating the internal clock signals is provided in the semiconductor device. A typical clock generation circuit is a phase locked loop (PLL) or a delay locked loop (DLL).
Control methods for producing the internal clock signals using the PLL or the DLL may be classified as an analog-based method or a digital-based method. The analog-based method uses a voltage controlled oscillator (VCO), while the digital-based method uses a voltage controlled delay line (VCLD).
FIG. 1 is a block diagram illustrating a conventional PLL.
Referring to FIG. 1, the PLL includes a phase/frequency detection unit 110, a charge pump unit 120, a loop filter unit 130, a voltage controlled oscillation unit 140, and a clock division unit 150.
The phase/frequency detection unit 110 produces an up-detection signal DET_UP and a down-detection signal DET_DN which correspond to a phase/frequency difference between a reference clock signal CLK_REF and a feedback clock signal CLK_FB. The charge pump unit 120 generates charge current or discharge current in response to the up-detection signal DET_UP and the down-detection signal DET_DN. The loop filter unit 130 produces an oscillation control voltage signal V_CTR which has a voltage level corresponding to the charge current or discharge current generated by the charge pump unit 120. The voltage controlled oscillation unit 140 produces a PLL clock signal CLK_PLL which has a frequency corresponding to the oscillation control voltage signal V_CTR. The clock division unit 150 divides the PLL clock signal CLK_PLL to generate the feedback clock signal CLK_FB. Finally, the feedback clock signal CLK_FB is fed back to the phase/frequency detection unit 110.
FIG. 2 is a circuit diagram illustrating the phase/frequency detection unit 110 of FIG. 1.
Referring to FIG. 2, the phase/frequency detection unit 110 includes an up-detection signal generation unit 210, a down-detection signal generation unit 220, and a reset unit 230.
The up-detection signal generation unit 210 generates the up-detection signal DET_UP in response to the reference clock signal CLK_REF and a reset signal RST. The down-detection signal generation unit 220 generates the down-detection signal DET_DN in response to the feedback clock signal CLK_FB and the reset control signal RST. The reset unit 230 generates the reset control signal RST in response to complementary signals of the up-detection signal DET_UP and the down-detection signal DET_DN.
FIG. 3 is a waveform diagram illustrating an operation of the phase/frequency detection unit 110 of FIG. 2.
Here, it is assumed that the reference clock signal CLK_REF has a frequency substantially the same as that of the feedback clock signal CLK_FB while the reference clock signal CLK_REF has a phase different from that of the feedback clock signal CLK_FB.
Referring to FIGS. 2 and 3, the up-detection signal DET_UP transitions to a logic high level in response to a rising edge of the reference clock signal CLK_REF, and the down-detection signal DET_DN transitions to a logic high level in response to a rising edge of the feedback clock signal CLK_FB. The reset control signal RST has a high logic level when complementary signals of the up-detection signal DET_UP and the down-detection signal DET_DN are both at a logic low level. Further, both the up-detection signal DET_UP and the down-detection signal DET_DN transition to a logic low level in response to a falling edge of the reset control signal RST. Therefore, the up-detection signal DET_UP and the down-detection signal DET_DN have different pulse widths according to a phase difference between the reference clock signal CLK_REF and the feedback clock signal CLK_FB.
Referring back to FIG. 1, the up-detection signal DET_UP and the down-detection signal DET_DN are transferred to the charge pump unit 120, and the charge pump unit 120 generates the charge current or the discharge current for a duration corresponding to a difference between the pulse width of the up-detection signal DET_UP and the pulse width of the down-detection signal DET_DN. Subsequently, the loop filter unit 130 produces the oscillation control voltage signal V_CTR which has a voltage level corresponding to the charge current or discharge current, and the voltage controlled oscillation unit 140 produces the PLL clock signal CLK_PLL which has a frequency corresponding to the oscillation control voltage signal V_CTR. Finally, the feedback clock signal CLK_FB is fed back to the phase/frequency detection unit 110 through the clock division unit 150.
Through repeated detections, the PLL outputs the PLL clock signal CLK_PLL which is synchronized with the reference clock signal CLK_REF. The process of synchronizing the reference clock signal CLK_REF and the PLL clock signal CLK_PLL is called a “phase/frequency locking” operation.
As described above, the phase/frequency locking operation of the conventional PLL is performed such that the charge pump unit 120 operates for a duration according to the pulse widths of the up-detection signal DET_UP and the down-detection signal DET_DN.
Meanwhile, in order for the PLL to output the PLL clock signal CLK_PLL having a desired frequency, a certain amount of time is required to perform the phase/frequency locking operation. In general, this amount of time is called a “locking” time. That is, the PLL is designed to produce the desired PLL clock signal CLK_PLL after the locking time elapses. After such desired PLL clock signal CLK_PLL is generated, a semiconductor device may use the PLL clock signal CLK_PLL as an internal clock signal. Accordingly, to order to secure a faster circuit operation of the semiconductor device, decreasing the locking time of the PLL is desired.